1. Field of the Invention
The present invention relates to a method for generating a periodic electric signal with a phase dependent upon a control signal by means of a weighted superposition of several input signals, which have a specified frequency but different input signals phases, whereby the weighted superposition is applied to a parallel arrangement of adjustable transconductance stages which are each adjusted by the control signal and to each of which one of the input signals is supplied.
Further, the invention relates to a circuit arrangement for carrying out such method.
Such signal generation may, for example, be employed in the so-called recovery of clock signals.
2. Description of the Prior Art
Such a method and such a circuit arrangement are known, for instance, from the article by Yueming Jiang and Alessandro Piovaccari, “A compact phase interpolator for 3.125G Serdes Application”, SSMSD 2003, IEEE, pages 249 to 252, 2003.
With the known method, as shown in FIG. 3 of this publication, 12 input signals are initially generated with a fixedly predetermined frequency, but with input phases distributed equidistantly over the 360° range. Then two input signals adjacent to one another with regard to their phase are selected and subjected to a “fine interpolation” in order to generate the desired output signal with the specified frequency and a phase which lies between the input phases of the two selected input signals.
The switching arrangement used for this phase interpolation is illustrated in FIG. 5 of the publication and comprises a parallel arrangement of adjustable transconductance stages (transistor pairs) for generating the output signal through a weighted superposition of the two selected input signals, whereby an adjusting current outputted by a digital/analog converter is applied to each of the transconductance stages, and whereby further one of the two input signals is directed to the transconductance stages (as transconductance input voltage). With this arrangement the digital/analog converter supplies, as it were, the weighting factors for the weighted superposition of the two input signals, which is performed by the transconductance stages. The currents supplied by the transconductance stages are brought together (superimposed) and jointly guided across a resistance load, so that eventually, the desired output signal is provided at the resistance load as a voltage drop. A control signal supplied to the digital/analog converter in a thermometer coding with 8 bits causes the total bias current of the two transconductance stages to be divided at ratios of 8:0, 7:1, 6:2, 5:3, 4:4, 3:5, 2:6, 1:7 or 0:8 (depending upon the state of the control signal).
This known phase interpolation has a number of disadvantages.
A first disadvantage is that the correlation between the phase of the output signal and the settings of the transconductance bias currents (adjusting currents) is not linear. The non-linearity increases, the more the phase difference increases between the two input signals used in the interpolation. This can be illustrated using as an example a circle which has straight lines drawn through the centre of the circle and through subdividing points located equidistantly at a secant of the circle, which intersect the arc of the circle at points which, as regards the angle, are only approximately equidistant (this problem will be explained again below with reference to FIG. 2).
The linearity of the phase interpolation can be improved in a simple way by providing a larger number of input signals of the plurality of input signals. But in practice this is only possible up to a point due to the amount of complexity of the circuit arrangement needed.
A further major problem often experienced in practice results from the fact that transductance stages arranged in parallel influence each other to a greater or lesser extent leading to a considerable falsification of the output phase. A particular problem is that the extent of this falsification is dependent upon the “weighting ratio” of the two input signals involved. In particular this extent is different for “extreme weightings” (such as 8:0 and 0:8) compared to “medium weightings” (such as 4:4). With the circuit topology of the above mentioned publication illustrated in FIG. 5 of the same, parasitic capacities between the gate and drain terminals of the transconductance transistors are a contributor to this disadvantageous effect. The drain potential is influenced more or less by the gate potential via this capacitive coupling, whereby the extent of the influence depends upon the phase difference between gate potential and drain potential.